Engineering Group, Engineering Group > Hardware Engineering
General Summary
Job Description - 5+ year RTL designer
We are looking for a highly motivated RTL Design Engineer with 5+ years of experience in front-end ASIC/SoC design. The candidate will be responsible for micro-architecture development, RTL implementation, and quality signoff activities including Lint and CDC analysis. Experience with synthesis and timing constraints development is highly desirable. The role involves close collaboration with architecture, verification, DFT, and physical design teams to deliver high-quality silicon.
Key Responsibilities
Develop detailed micro-architecture specifications from high-level architectural requirements.
Design and implement synthesizable RTL using Verilog/SystemVerilog.
Participate in design reviews and ensure design quality and compliance with coding guidelines.
Perform RTL quality checks including:
Lint analysis and cleanup
CDC/RDC analysis and closure
FSM and structural checks
Develop and maintain design documentation including micro-architecture and interface specifications.
Work closely with verification teams to define verification plans and resolve functional issues.
Support synthesis, timing analysis, and timing closure activities.
Develop and review SDC constraints for block-level and subsystem-level designs.
Analyze and debug issues across simulation, synthesis, and implementation stages.
Collaborate with DFT and physical design teams for successful integration and tapeout.
Minimum Qualifications
Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.
OR
Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.
OR
PhD in Computer Science, Electrical/Electronics Engineeri
📌 RTL Design Engineer, Sr Lead (Bengaluru)
🏢 Qualcomm
📍 Bengaluru
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