As a Verification engineer, should have the hands-on experience related to block level, sub-system level and chip top level verification.
Development and working with object-oriented verification languages (System Verilog, UVM)
Have background in Mixed Signal devices.
Able to handle multiple blocks (good at time management).
Good at debugging design and environment related issues.
Should work closely with the designers to understand the design changes and implement the same in Verification.
Should be good with scripting languages.
Essential Functions
Should be good at Digital basics.
Develop environment and tests for block level verification and extend the same to block and chip top level verification.
Good understanding of RAL, Code coverage and functional coverage and implementing the same
Scripting using Perl, Python and Shell
Simulations using gate level netlist at various PVT corners.
Generation of vcd files for power analysis.
Good understanding of DFT concepts and running ATPG simulations
Working with analog and architecture teams to handle integration of netlist and models into test environment.
Usage of FPGA based validation platform in the lab.
Handling of bring-up and characterization lab activities.
Support customer queries and their debug activities.
Ability to work and communicate effectively in a team and to be able to multi-task effectively in a quick-paced work environment.
Requirements
A technology-related bachelor’s degree or higher with 8-15 years of related experience in verification roles.
Experience in mixed signal devices.
Skills: perl, python and shell,ral,verification engineer,mixed signal devices,systemverilog,universal verification methodology (uvm)