Design For Test Engineer (Hyderabad)

Design For Test Engineer (Hyderabad)

13 Aug
|
EdgeSilica Private
|
Hyderabad

13 Aug

EdgeSilica Private

Hyderabad

Company Description EdgeSilica Private Limited is a semiconductor services company that delivers high-quality VLSI design and engineering solutions to global customers. The organization specializes in physical design, design verification, SoC and IP integration, and system software, helping clients accelerate time-to-market while maintaining strong engineering standards. EdgeSilica supports startups, fabless companies, and product organizations across the semiconductor ecosystem with process-driven execution and customer-first engagement. Teams are trained on industry-standard EDA tools and follow best practices in design quality, scalability, and confidentiality. The company focuses on reliable, scalable, and future-ready semiconductor engineering services, built for long-term partnerships.
Role Description The Design For Test (DFT) Engineer will design, implement, and verify test architectures for complex SoCs and IP blocks, ensuring robust testability and high fault coverage. Day-to-day responsibilities include developing scan, BIST, and boundary scan strategies,



integrating DFT features into the design flow, and collaborating with front-end, physical design, and verification teams to achieve sign-off-quality test solutions. The role involves writing and reviewing specifications, creating test plans, analyzing coverage reports, and supporting silicon bring-up and production test optimization. The DFT Engineer will also contribute to methodology improvements, documentation, and best practices across projects. This is a full-time, on-site role based in Hyderabad.
Qualifications
Solid knowledge of DFT concepts such as scan insertion, ATPG, MBIST, LBIST, and boundary scan, with experience applying them to complex SoCs.
Hands-on experience with industry-standard EDA tools for DFT implementation and verification (e.g., Tessent, Synopsys, Cadence or equivalent).
Solid understanding of digital design, RTL, and synthesis flows, including timing, constraints, and physical

📌 Design For Test Engineer (Hyderabad)
🏢 EdgeSilica Private
📍 Hyderabad

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