About the Company

We are looking for an experienced DFT Lead with strong expertise in Design-for-Test implementation for complex SoC and ASIC designs. The candidate will be responsible for planning, implementing, verifying, and signing off DFT structures across multiple blocks and full-chip designs. The role requires robust technical knowledge of scan architecture, ATPG, memory testing, test compression, boundary scan, and physical-design-aware DFT implementation. The candidate will also provide technical leadership, guide junior engineers, and collaborate with RTL, synthesis, physical design, verification, and product engineering teams.

About the Role

DFT Lead

Location: Bangalore, Chennai ,Malaysia and Japan

Experience: 7+ Years and 4+ years

Employment Type: Full-Time

Role: DFT Lead / Senior DFT Engineer

Responsibilities

Define and implement the DFT architecture for block-level and full-chip SoC designs.
Perform scan insertion, scan stitching, scan compression, and scan reordering.
Develop and implement ATPG strategies for stuck-at, transition, path-delay,



and other fault models.
Implement and verify MBIST, LBIST, IJTAG, JTAG, and boundary-scan architectures.
Perform DFT rule checks, debug violations, and ensure design readiness for ATPG.
Generate and validate production-quality test patterns.
Analyse ATPG coverage and improve fault coverage through test-point insertion and design enhancements.
Perform pattern simulation at RTL, gate level, and timing-annotated netlist levels.
Debug scan-chain failures, pattern mismatches, X-propagation issues, and coverage gaps.
Work closely with physical design teams on scan-chain placement, scan reordering, congestion, timing, and routing issues.
Support low-power DFT implementation for designs involving multiple power domains, isolation, retention, and power gating.
Perform DFT timing analysis and resolve setup, hold, and clock-related issues in test mode.
Support post-silicon bring-up, silicon debug, yield analysis, a

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