We are seeking a highly motivated Physical Design Engineer to drive the physical implementation and timing closure of complex, low-power SoCs targeted for the IoT and MCU markets. The ideal candidate will play a key role in achieving design objectives related to area, performance, and power while ensuring high-quality silicon implementation.
Your role
Key responsibilities in your new role :
Drive physical design and timing closure activities for hierarchical blocks and full-chip SoC designs, meeting aggressive area, performance, and power (PPA) targets.
Own and execute various stages of the physical design flow, including:
Floorplanning and I/O planning
Package co-design
Power grid design
Placement and routing
Clock Tree Synthesis (CTS)
Timing optimization and closure
Static and Dynamic IR drop analysis
Physical verification and signoff checks
Implement and optimize low-power design methodologies, including designs with multiple voltage domains, power islands, and advanced power-reduction techniques.
Collaborate closely with cross-functional teams to ensure seamless integration of package, design, and implementation requirements.
Develop, enhance, and drive physical design methodologies and automation flows to continuously improve Quality of Results (QoR), productivity, and design efficiency.
Analyze and resolve complex implementation challenges while ensuring design robustness, scalability, and manufacturability.
Contribute to best practices, technical innovations, and continuous improvements within the physical design organization.
Ideal Candidate Profile
Robust hands-on experience in end-to-end physical design and timing closure for advanced SoCs.
Deep understanding of low-power implementation techniques, including multiple voltage and power domains.
Good knowledge of I/O planning and package co-design considerations.
Proven ability to drive design closure and improve QoR through methodology and flow enhancements.
Self-driven, detail-oriented, and capable of wo