Memory Layout Design Engineer, Staff (Noida)

Memory Layout Design Engineer, Staff (Noida)

13 Aug
|
Synopsys
|
Noida

13 Aug

Synopsys

Noida

Date posted 07/13/2026
Category EngineeringHire Type EmployeeJob ID 17875Remote Eligible NoDate Posted 07/13/2026:
Memory Layout Design Engineer, Staff:
We Are:
Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D; capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

You Are:
You have spent years deep in the details of custom memory layout, and you know that the difference between a memory compiler that ships and one that stalls out is usually in how you handled density, matching, and DRC closure three weeks before tape-out. You think in layers, in device symmetry, in parasitic trade-offs. When a circuit designer hands you a schematic, you see not just what they drew but what they meant,



and you know how to translate that intent into a layout that works across process corners and actually manufactures.

You do not wait for someone to tell you the DRC is broken. You catch it, you debug it, and you drive the fix. You have migrated designs across technology nodes and lived through the surprises that come with FinFET scaling. You can sit with a junior engineer and explain why their routing choice will create an antenna violation, and you can sit with a methodology team and push back when an automation script does not account for real layout constraints.

At Synopsys, you will work on memory IP that powers chips across the industry. The work is technical, the problems are real, and what you design will ship.

What You'll Be Doing:
- Design and own custom layouts for SRAM, Register Files, ROM, and related memory compiler IP blocks from floorplan through final signoff
- Execute and close DRC, LVS, ERC, antenna, density, and reliability checks using Virtuoso a

📌 Memory Layout Design Engineer, Staff (Noida)
🏢 Synopsys
📍 Noida

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