Quadric is redefining edge AI with the industry's first General Purpose Neural Processing Unit (GPNPU), enabling developers to run both neural network inference and conventional C++ code on a single programmable architecture. Our technology powers intelligent edge devices across automotive, industrial, robotics, and embedded systems.
Founded by technologists from MIT and Carnegie Mellon, Quadric is a well-funded growth-stage semiconductor IP company with a growing licensing business.
The Chance
Quadric is building a revolutionary new processor-based SoC architecture. As a
Senior Design Verification Engineer
, you will join the ground floor of our chip design team, taking technical leadership in architecting and building our SoC-level verification environment from scratch. You will collaborate closely with architects, hardware engineers, and software teams to ensure high quality and complete verification coverage for our next-generation GPNPU-based SoCs.
What You'll Do
Testbench Architecture & Test Plan Development
- Architect and build novel,
scratch-built testbenches for SoC-level verification of our GPNPU-based SoCs.
- Collaborate cross-functionally with architects, HW designers, and SW teams to document comprehensive verification test plans.
- Implement scalable testbenches using commercial Verification IP (VIP) and/or internal software utilities.
Test Execution & Verification Coverage
- Develop directed and random drivers, as well as assembly or C++ programs, to efficiently stress-test SoC subsystems and integration.
- Verify complex SoC subsystems, including 3rd-party IP (e.g., NoC, PCIe/UCIe, DDR).
- Leverage VCS and Verilog/C Co-Simulation environments alongside assembly programming and Python scripting to execute test suites.
- Track, analyze, and communicate verification progress across teams using functional and code coverage metrics.
What Success Looks Like
Within your first 6-12 months, you'll:
- Build out and deploy a fully fu