Subject: ACL Digital Hiring - Locations, Skills | Chance at ACL Digital (Subsidiary of ALTEN Group)

Greetings from ACL Digital, a subsidiary of ALTEN Group We are expanding our engineering team and looking for experienced FPGA Design Engineers to work on cutting-edge FPGA development and verification projects. Interested candidates can apply directly or refer their friends by sharing their updated resumes for these roles

Below are the concise job details for our open position:

FPGA Design & Verification Engineer
- Location: Hyderabad
- Notice Period: 0 to 30 Days (Immediate joiners preferred)
- Experience: 4 - 15 Years
- Work Mode: Work from Office

CategoryDetailsRole OverviewDrive end-to-end FPGA development, architecture implementation, simulation, static timing analysis (STA), and on-hardware debugging using industry-standard tools.Key

Responsibilities
- Design, develop, and integrate complex RTL logic for target FPGA architectures.
- Perform pre/post-synthesis simulation debugging and verification.
- Run Static Timing Analysis (STA),



set up timing constraints (SDC), and close timing bottlenecks.
- Execute hands-on hardware bring-up, signal integrity checks, and real-time on-chip debugging using ILA.
- Collaborate with cross-functional software, board, and verification teams for seamless system integration.

Required Skills
- 4-15 years of hands-on experience in FPGA design and development (Xilinx, Altera/Intel, or Microchip).
- Proficiency in RTL coding (Verilog, SystemVerilog, or VHDL).
- Strong experience in software tools and simulation debugging using QuestaSim, ModelSim, or VCS.
- Hands-on expertise in on-chip hardware debugging using ChipScope / Integrated Logic Analyzer (ILA).
- Deep knowledge of Static Timing Analysis (STA), constraint creation, and timing closure.

Preferred Skills
- Exposure to standard bus protocols (AXI, APB, AHB, PCIe, or Ethernet).
- Experience with TCL or Python scripting for automation.

📌 Fpga Engineer (Hyderabad)
🏢 ACL Digital
📍 Hyderabad