Responsible for planning and execution of all aspects of Physical Design including Synthesis Floor planning Place and Route Clock Tree Synthesis IP integration Extraction Physical Verification and taking blocks to the closure In your new role you will Responsible for planning and execution of all aspects of Physical Design including Synthesis Floor planning Place and Route Clock Tree Synthesis IP integration Extraction Physical Verification and taking blocks to the closure Design Application Engineering DAE will be responsible for supporting project teams using Infineon Design System Flows Design Package Design assistance You will be the first point of contact for project teams in case of issues and will work to achieve the highest customer interaction Responsible for automation of manual processes including design flow design package qualification mechanisms generation of test reports dashboards etc and providing automation requirements for reducing manual steps in qualification The candidate will have an internal drive to work with design and EDA vendors to solve issues and adopt new flows The candidate should have reasonable ability to automate design work by means of script programming e g Tcl tk Perl or Python Your Profile You are best equipped for this task if you have The candidate should have a minimum of 6 years of relevant working experience in Physical Design implementation areas including Synthesis LEC and PnR as well as valuable exposure to signoff areas particularly power timing and IR signoff One should have a deep understanding of and be able to be cater to design concerns across semi-custom design flows including RTL analysis synthesis LEC Place and Route STA EM IR and physical verification One should be able to identify flow gaps and provide automation on need base to perform all design activities in the most efficient and correct-by-construction way One should be able to evaluate solutions from multiple available options and be able to perform trade-offs between technical features Analyse the results and any inconsistency issues to be reports via bug tracking system One will work with R D in Infineon globally and EDA tool vendors to resolve issues across semi-custom design flows One will coordinate with IT and EDA tool license teams to provide an infrastructure aligned with project needs One should have exposure to basic version management using any of Clearcase Perforce Cliosoft Git You should possess excellent communication skills to interact effectively with peers and customers in a clear and honest manner with consistent and open to learning new technical areas if the need arises You should define and monitor key test metrics build regression status reporting dashboard Develop and execute QA test plans verification methodology test strategies for digital block chip level to maximize the coverage of features methodology supported in the technologies Design Flows Contact swati gupta infineon com WeAreIn for driving decarbonization and digitalization As a global leader in semiconductor solutions in power systems and IoT Infineon enables game-changing solutions for green and efficient energy clean and safe mobility as well as smart and secure IoT Together we drive innovation and customer success while caring for our people and empowering them to reach ambitious goals Be a part of making life easier safer and greener Are you in We are on a journey to create the best Infineon for everyone This means we embrace diversity and inclusion and welcome everyone for who they are At Infineon we offer a working environment characterized by trust openness respect and tolerance and are committed to give all applicants and employees equal opportunities We base our recruiting decisions on the applicants experience and skills about our various contact channels Please let your recruiter know if they need to pay special attention to something in order to enable your participation in the interview process for more information about Diversity Inclusion at Infineon