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As an STA Engineer, you will drive timing analysis and closure for complex low-power SoCs, ensuring designs meet performance and power targets across multiple modes and operating conditions. You will develop and validate timing constraints, perform pre- and post-layout timing signoff, and resolve critical timing challenges.
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Your role
Key responsibilities in your new role
Responsible for STA and Timing Closure of complex, low power SoCs targeted for IOT and MCU markets.
Ownership of constraints development for functional/test modes at pre and post layout stage.
Opportunity to work on IO timing closure for critical interfaces like Serial Peripherals and External Memory Interfaces.
Timing analysis and convergence of large hierarchical design across multiple modes and corners.
Interact with RTL and DFT teams on timing feasibility and performance assessment.
Work closely with physical design team for timing/SI closure.
Your profile
Qualifications and skills to help you succeed
Entrepreneurial Knowledge:
B.Tech or M.Tech relevant work experience and specialization in VLSI design.
Strong hands-on technical experience in constraints development, timing analysis/closure of SoCs.
Experience in low-power synthesis and equivalence checks will be a plus.
Expert user of industry standard tools for timing signoff.
Experience in scripting languages (shell, perl, tcl) and Make flow.
Must be well organized, methodical and detail oriented.
Soft Skills: -
Robust commitment and determination in area of expertise.
Takes initiatives and overcomes challenges through creativity and innovation.
Coordinates with colleagues and actively shares expertise with others.
Shares information comprehensively and effectively.
Cooperates across boundaries and appreciates the contributions of other people.
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