Lead RTL Design Engineer (ASIC)

Location: Chennai, Tamil Nadu

Experience: 6 to 9 Years

6 to 9 Years of experience in Synthesis, Constraints and interface timing Challenges. Solid Domain Knowledge on RTL Design, implementation, and Timing analysis.

Experience with RTL coding using Verilog/VHDL/System Verilog.

Experience in micro-architecture & designing cores and ASICs.

Exposure in scripting (Pearl/Python/TCL).

Solid debugging capabilities at Synthesis, timing analysis & implementation

Collaborate closely with cross-function team to research, design and implement performance, constraints and power management strategy for product roadmap.

ACL Digital, part of the ALTEN Group, is a trusted AI-led, Digital & Systems Engineering Partner driving innovation by designing and building intelligent systems across the full technology stack — from chip to cloud. By integrating AI and data-powered solutions, we help enterprises accelerate digital transformation, optimize operations, and achieve scalable business outcomes.

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🏢 ACL Digital
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