ob Description:

We are looking for an experienced Senior Engineer Design Verification with solid hands-on expertise in Logic Design Verification, SystemVerilog, UVM, Functional Coverage and SystemVerilog Assertions (SVA).

The candidate will be responsible for developing and executing verification strategies, building UVM-based verification environments, developing coverage-driven tests, debugging design issues and working closely with Logic Design Engineers.

Key Responsibilities:
Develop requirement-oriented verification and test plans
• Develop and maintain SystemVerilog UVM verification environments
• Develop and integrate UVCs
• Develop coverage-driven tests and drive functional coverage closure
• Develop and implement SystemVerilog Assertions (SVA)
• Perform stress and performance testing
• Debug design and verification issues and identify root causes
• Work closely with Logic Design Engineers on specifications and verification requirements
• Track verification progress and report project status, risks and challenges
• Support CI and verification infrastructure as required





Required Skills & Experience:
6–8 years of overall experience in Design Verification
• 6+ years of hands-on experience in Logic Design Verification
• 3+ years of hands-on experience in SystemVerilog UVM
• Robust hands-on experience with SystemVerilog
• Strong knowledge of UVM methodology and UVC development/integration
• Strong experience in SystemVerilog Assertions (SVA)
• Strong experience in Functional Coverage and Coverage Closure
• Experience in ASIC and/or FPGA verification
• Positive scripting skills in Python, Perl, TCL or BASH
• Good working experience with Linux
• Experience with version-control tools such as Git, SVN, CVS, Perforce or ClearCase
• Minimum 2 years of experience working on international projects
• Strong debugging and problem-solving skills

Qualification:

Bachelor’s degree in Computer Science, Electrical Engineering, Electronics Engineering, Software Engineering or a related discipline.

📌 Senior Engineer Design Verification Bengaluru (India)
🏢 Brain Links and Resources
📍 India