Job DescriptionBelow is the JD for RTL engineers. We need to build robust RTL team.
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Minimum 8+ years of work experience in ASIC RTL Design, Synthesis, STA & FV N
Experience in Logic design/micro-architecture/RTL coding is a must. N
Must have hands on experience with design and integration of complex multi clock domain blocks N
Experience in Verilog/System-Verilog is a must. N
Should have knowledge of AMBA protocols - AXI, AHB, APB, clocking/reset/debug architecture N
Hands on experience in Multi Clock designs, Asynchronous interface is a must. N
Experience in using thetools in ASIC development such as Lint, CDC, Design compiler and Primetime is required. N
Work closely with the Design verification and validation teams for pre/post Silicon debug N
Hands on experience in Low power design is preferable N
Experience in Synthesis/ Understanding of timing concepts for ASIC is must N

📌 Rtl Design Lead Bengaluru (India)
🏢 L&T Technology Services
📍 India