Job DescriptionJob Role: Memory Layout Design Engineer (2 – 10 years exp.)
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Role: Execute Layout Design of SRAM/CAM/RF compiler memories 3nm and lower technology.n
Responsibilities: Development of key building blocks of memory architecture such as Row Decoder, IO, Control. Skilled in pitched layout concepts, floor planning for Placement, Power and Global Routing. Knowledge of EM/IR requirements. Compiler level integration, verification of Compiler/Custom memories. Should possess valuable knowledge on CMOS fabrication process, foundries and challenges in latest technology nodes.n

nSkills : Well experienced in using industry standard EDA tools like Cadence Virtuoso, Mentor Graphics Caliber etc. Good problem solving and logical reasoning skills. Positive communication skills required.
nBehavioral Traits: Ability to follow established procedures and work in a distributed team workplace. Work independently to deliver high quality results on time.

📌 Memory Layout Design Engineer Karnataka
🏢 Mirafra Technologies
📍 Karnataka