Job DescriptionLead Verification Engineer
nExperience: 7+ years
nLocation: Hyderabad
nJob Description:
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Work as a member of a geographically distributed verification team to verify next-generation ASIC and FPGAsn
Develop testplans, implement testbenches, create testcases, and ensure functional coverage closuren
Handle regression testing and contribute to verification infrastructure developmentn
Develop both directed and random verification testsn
Debug test failures, identify root causes, and work with RTL and firmware engineers to resolve design defects and test issuesn
Review functional and code coverage metrics, modify or add tests or constrain random tests to meet coverage requirementn
Collaborate with design, software and architecture teams to verify design under testn

nPreferred Experience:
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Proficient in IP-level FPGA and ASIC verificationn
Knowledge of PCIe, CXL or other IO protocol is preferredn
Proficient in Verilog/SystemVerilog,



and scripting languages such as Perl or Pythonn
Hands-on experience with SystemVerilog and UVM is mandatoryn
Experience in developing UVM-based verification testbenches, processes, and flowsn
Solid understanding of design flow, verification methodology, and general computational logic design and verificationn

nAbout Company
nACL Digital, a leader in digital engineering and transformation, is part of the ALTEN Group. At ACL Digital, we empower organizations to thrive in an AI-first world. Our expertise spans the entire technology stack, seamlessly integrating AI and data-driven solutions from Chip to cloud. By choosing ACL Digital, you gain a strategic advantage in navigating the complexities of digital transformation. Let us be your trusted partner in shaping the future.

📌 Verification Lead Hyderabad
🏢 ACL Digital
📍 Hyderabad