We are hiring for one of our reputed clients for the following position. If you're interested and your experience matches the requirement, we'd love to hear from you.
Position: Verification Engineer 3
Experience: 5-9 Years
Location: Bangalore
Contract : 12 Months
:
Mandatory Skills Top 3
1. Strong SystemVerilog (SV) skills
2. Strong proficiency in UVM methodology
3. Hands-on experience in DDR or other PHY verification – Mandatory
Good-to-Have Skills
- Experience with Gate-Level Simulation (GLS).
- Experience with Co-Simulation environments.
- Hands-on experience with Formal Verification.
- Experience with Assertion-Based Verification (ABV) and SystemVerilog Assertions (SVA).
- Knowledge of functional and code coverage methodologies.
- Experience working with complex verification environments and large-scale regressions.
Required Qualifications
- B.E./B.Tech./M.E./M.Tech. in Electronics & Communication Engineering or a related field.
- 5–7 years of relevant experience in ASIC/SoC verification.
- Strong hands-on experience with SystemVerilog and UVM.
- Proven experience in debugging UVM-based regression failures.
- Experience developing and executing verification tests in a UVM environment.
- DDR or PHY verification experience is mandatory.
- Strong analytical, debugging, and problem-solving skills.
- Good communication and collaboration skills.erification and assertion-based methodologies (positive to have)