Company Description

Sandisk understands how people and businesses consume data and we relentlessly innovate to deliver solutions that enable today’s needs and tomorrow’s next big ideas. With a rich history of groundbreaking innovations in Flash and advanced memory technologies, our solutions have become the beating heart of the digital world we’re living in and that we have the power to shape.

Sandisk meets people and businesses at the intersection of their aspirations and the moment, enabling them to keep moving and pushing possibility forward. We do this through the balance of our powerhouse manufacturing capabilities and our industry-leading portfolio of products that are recognized globally for innovation, performance and quality.

Sandisk has two facilities recognized by the World Economic Forum as part of the Global Lighthouse Network for advanced 4IR innovations. These facilities were also recognized as Sustainability Lighthouses for breakthroughs in efficient operations. With our global reach, we ensure the global supply chain has access to the Flash memory it needs to keep our world moving forward.

Role Summary

Own the end-to-end PCIe system design for an NVMe SSD product line across client laptops and enterprise servers, from PHY/MAC review through ASIC/SoC integration, PCIe SFR/register analysis, and firmware design guidelines for robust link training, link transitions, low-power behavior. This role sits at the intersection of PCIe spec compliance, NVMe behavior, FW architecture, platform interoperability, and power/performance tuning.

Key Responsibilities

Own system‑level PCIe Gen5/Gen6 architecture from an NVMe SSD endpoint perspective

Define and review PCIe + NVMe integration across SSD products

PHY + MAC IP review, integration requirements and constraints

SoC/ASIC integration: clocks, resets, power domains, straps, lane mapping, sidebands

PCIe SFR + FW guidelines: flow control, LTSSM observability, power states, error handling

Link & low power transitions: DLRM, L1, L1SS, L0p, ASPM, clock-down, APST Coordination

Bring-up + debug: enumeration, speed negotiation, width detection, stability, AER/error recovery

Customer requirement tuning: latency/power, performance, reliability and consistency

Provide deep expertise in PCIe configuration and extended capability registers, including:

Link, power management, MSI/MSI‑X, AER, BARs, L1SS

Lead platform bring‑up and debug:

Enumeration, link training, speed negotiation, power states, error handling





Act as the technical authority for cross‑team and customer escalations

Qualifications

Detailed Responsibilities (End‑to‑End PCIe for NVMe SSD)

PHY/MAC IP Review (System Design Perspective)

Understand criteria for PHY/MAC/controller IP:

Gen5/Gen6 readiness, equalization capability, margining hooks, lane mapping flexibility

SRNS/SRIS tolerance, clocking modes, power management support

Observability: LTSSM state visibility, error counters, replay/NAK stats, equalization telemetry

Review IP documents

Reset sequences, compliance features, link speed change support

L1SS behavior, CLKREQ#/REFCLK control expectations

AER robustness, surprise down handling, hot/warm reset behavior

Specify platform-facing requirements:

Retimer/redriver compatibility assumptions (backplane/adaptor/cables)

ASIC/SoC Integration Ownership

Integrate PCIe subsystem with

Clocking: REFCLK handling, clock request gating, clock-down sequences

Resets: PERST# behavior, internal resets, warm/hot resets, FLR support as applicable

Power domains: retention strategies, wake sources, D-state coordination

Sidebands: WAKE#, CLKREQ#, presence detect patterns (platform dependent)

Define lane policy

x4 typical NVMe, lane reversal/polarity, width detection & recovery from degraded width

PCIe SFR / Register + FW Design Guidelines

Define a clean SFR map that FW uses for:

LTSSM control/observability (state, substate, timers, retries)

Link speed/width control and status (negotiated vs target)

Low-power triggers: ASPM enable/disable, L1SS policy, L0p policy (if implemented)

Clock request & clock gating behavior (safe entry/exit rules)

Error logging counters (replay, NAK, ECRC, timeout, malformed TLPs)

Recovery controls: link disable/enable, retrain, directed speed change, error transparent policy

Provide FW runbooks

“What to do when”: training fails, width reduces, speed fallback, AER floods

Safe sequencing across power modes and APST transitions

Link Bring‑Up & Transitions (Sequence Ownership)

You’ll own/define the exact sequencing rules for:

Enumeration readiness

Ensure config space stability,



BAR mapping correctness, MSI/MSI-X readiness timing

Speed negotiation / Directed Speed Change

When to allow Gen5/Gen4 fallback; policy for stability vs performance

Width detection & recovery

Handling degraded width events (x4 → x2) and reporting/telemetry

Link power management

ASPM policy and its constraints with NVMe latency targets

L1 entry/exit triggers and guard timers

L1 Substates (L1.1/L1.2) enablement conditions, wake sources, and clock requirements

DLRM handling (as applicable to platform/system) with safe NVMe readiness on resume

L0p (if supported) and interaction with performance bursts

Clock down / clock request

Define clock request gating conditions, and safe “no transactions in flight” criteria

NVMe APST alignment

Coordinate NVMe power states (APST) with PCIe L-states so you don’t create:

long resume latencies (client)

link instability under load (enterprise)

Platform Interoperability

Own differences across laptop and server:

Client: aggressive power policies, fast resume, frequent idle entry/exit, D3hot/cold patterns

Enterprise: stable performance, high queue depth, error containment, hot-plug-ish behaviors on some platforms

Validate across

Multiple root complexes, BIOS implementations, OS stacks

Additional Information

Sandisk thrives on the power and potential of diversity. As a global company, we believe the most effective way to embrace the diversity of our customers and communities is to mirror it from within. We believe the fusion of various perspectives results in the best outcomes for our employees, our company, our customers, and the world around us. We are committed to an inclusive environment where every individual can thrive through a sense of belonging, respect and contribution.

Sandisk is committed to offering opportunities to applicants with disabilities and ensuring all candidates can successfully navigate our careers website and our hiring process. Please contact us at [email protected] to advise us of your accommodation request. In your email, please include a description of the specific accommodation you are requesting as well as the job title and requisition number of the position for which you are applying. Job Type (exemption status): Exempt position - Please see related compensation &

benefits details below

Business Function: Memory Systems Design

Work Location: Bangalore Cosmos Office--LOC_WDT_Bangalore Cosmos Office

📌 Staff Memory Systems Design Engineer (Bengaluru)
🏢 Sandisk
📍 Bengaluru