Lead role: 5 8 yrs range (3 position)

Role Responsibilities

- Includes definition and development of signoff methodology and corresponding implementation solution.

- Flow for STA, Crosstalk Delay and Crosstalk Noise analysis for digital ASIC/SoCs.

- Full chip timing constraints development, full chip / Sub-System STA and Signoff for a complex, multi-clock, multi-voltage SoC.

- Streamlining the timing signoff criterions, timing analysis methodologies and flows.

- Analyze and incorporate advance timing signoff flows (AOCV, POCV Based STA, IR Drop aware STA) into SoC timing signoff flow.

- Work for Systems and Architecture, SoC Integration, Verification, DFT, Mixed Signal, IP owners, Synthesis, Place Route and other local/remote teams to address the design challenges in the context of the block, chip, and overall system.

- Concepts of CRPR, clock paths analysis and tweaks to meet timing.

- Multi Corner and MultiMode analysis.

- Close timing at SignOff corners covering the entire modes, delay corners for cells and interconnects.

Desired Qualification

- University degree (B.Tech/ M.Tech) in Electronics/ Electrical Engineering or similar. Other candidates will be considered if they have relevant experience.

- 3-7 Years of engineering experience primarily focussing on Physical design.

- Robust interpersonal skills, excellent verbal and written communication skills.

- Self-motivated and willing to take up additional responsibilities to contribute to the team s success.

- Strong analytical, problem solving and debugging skills.

Desirable Experience

- SoC/Chip level Timing closure and Signoff of high speed complex design with multiple clocks and power domains with minimal supervision.

- Working experience on lower technology nodes like 40nm and below till 14nm/10nm.





- Expertise in developing and owning Block and full chip Timing Constraints for complex, multi-clock, multi-voltage SoCs.

- Expertise in I/O constraints developments for Industry standard protocols would be an advantage.

- Good understanding of deep submicron parasitic effects, crosstalk effects, newer statistical timing approaches.

- Work with the Implementation team in having the SignOff Timing closure done.

Embedded Requirements

JD1

- Solid understanding of object-oriented design in C and C++, embedded platform.

- Knowledge of IBM Rational Rhapsody and development using UML.

- Knowledge of serial communication protocols, especially J1939, Hands on experience of CANalyzer.

- Experience using embedded debug tools such as JTAG/ICE debuggers, oscilloscopes.

- Familiarity with Git or ClearCase or any other version control tool in the agile software development process

JD2

- 802.11 protocol testing experience.

- Excellent knowledge of IEEE 802.11 WLAN protocol and standards (802.11a, b, g, n, ac, d, h, I, k, r).

- Experience with wireless trace tools required (Omni peek, Wireshark).

- Experience configuring and managing network infrastructure and WLAN devices like Access Points and Switches required.

- Experience configuring and testing and troubleshooting networking technologies, WLAN security protocols (802.1x, AES/CCMP, etc.).

- Excellent problem solving ability with experience in diagnosing complex system issues including strong debugging skills.

- Ability to work in a fast paced environment and be a positive team player.

- Bachelor s degree from an accredited college or university in Computer Science, Computer Engineering or similar.

Disclaimer: This job posting & Location has been aggregated from external source. Role details, content, and availability are subject to change. Applicants are advised to confirm the latest information directly on the company website before applying.

📌 STA Engineer (Bengaluru)
🏢 Bangalore Labs (BLRLABS)
📍 Bengaluru