Requirements

- Bachelor’s / Master’s degree in Electrical Engineering or Computer Science with 7-10 years of relevant experience or master’s degree in Electrical Engineering or Computer Science with 6-10 years of relavent experience.
- Verilog / System Verilog based verification experience at Subsystem and Full chip level.
- Experience with digital system based on AMBA Bus protocols like ACE/AXI/AHB/APB/CHI or similar complexity bus protocols.
- Experience with System Verilog Assertions with industry standard tools a plus
- Experience with Low Power Verification and power management flows.
- Experience with RTL, GLS level simulations
- Knowledge and experience working on PCIE/USB/DDR
- Experience in UVM/OVM based methodology Development.
- Multimedia Domain expertise.

Responsibilities

- Be part of a team to verify complex system on a chip designs. Interact with design engineers to identify significant verification scenarios.
- Create and enhance constrained-random verification environments using UVM/Sytem Verilog
- Create complex C/SV tests using reusable test libs
- Team player and mentor who is self-driven, motivated and guides a team of junior engineers
- Responsible for quality and timeliness of the team output

📌 SR. SOC DESIGN VERIFICATION ENGINEERS (Bengaluru)
🏢 Mettlesemi Systems and Technologies Private
📍 Bengaluru