14 Aug
|
Einfochips
|
Ahmedabad
14 Aug
Einfochips
Ahmedabad
Roles and Responsibilities :
- Design and develop testbenches using UVM (Universal Verification Methodology) for complex digital designs.
- Collaborate with cross-functional teams to identify requirements and create verification plans, test cases, and scenarios.
- Develop high-quality code coverage metrics to ensure thorough testing of IP blocks and SoCs (Systems on Chip).
- Analyze results, debug issues, and provide recommendations for improvement.
Job Requirements :
- 5-15 years of experience in design verification engineering with expertise in SOC verification.
- Solid understanding of UVM (Universal Verification Methodology) programming language.
- Experience working on complex digital designs at the block level or full chip level.
📌 Senior Design Verification Engineer (Ahmedabad)
🏢 Einfochips
📍 Ahmedabad