– ASIC/RTL Design Engineer

Work Location: Hyderabad

Experience: 4-6

Job Title: Engineering – ASIC/RTL Design Engineer

Job Summary

We are seeking a Senior Silicon Design Engineer with 4–6 years of experience in RTL design and SoC/subsystem integration. The ideal candidate will have robust expertise in integrating complex IPs into large-scale SoCs, working with AMBA-based interconnects, and delivering high-quality RTL through silicon production. This role requires close collaboration with architecture, verification, physical design, firmware, and validation teams to enable successful execution of subsystem and SoC development programs.

Key Responsibilities

Lead RTL development and integration of complex IPs and subsystems within SoC environments.

Drive subsystem-level design activities including integration, connectivity, clocking, reset architecture, and configuration management.

Develop and maintain synthesizable RTL in Verilog/SystemVerilog.

Implement and integrate AMBA-based interfaces (AXI, AHB, APB).

Own end-to-end integration of third-party and internally developed IPs.

Define and implement interconnect, clocking, reset, and data-flow architectures.





Collaborate with architecture teams to translate specifications into robust microarchitectures and RTL implementations.

Work closely with verification teams to debug simulation failures and close coverage goals.

Support synthesis, CDC/RDC analysis, timing closure, low-power implementation, and silicon bring-up activities.

Mentor junior engineers and contribute to design process improvements.

Required Skills & Qualifications

Bachelor’s/Master’s in Electrical, Electronics, or Computer Engineering.

4–6 years of experience in ASIC/SoC RTL Design and Integration.

Strong RTL development skills using Verilog/SystemVerilog.

Proven experience integrating multiple IPs into complex SoC/subsystem environments.

Strong understanding of:

AMBA AXI4/AXI4-Lite, AHB/APB protocols

Interconnect architectures

Clocking and reset strategies

Memory-mapped architecture

Knowledge of FSM design, pipelining, arbitration logic, performance optimization, CDC/RDC methodologies.

Experience with synthesis, timing analysis, lint, CDC, RDC, and static verification tools.

Strong debugging and problem-solving skills.

📌 RTL Engineer (Hyderabad)
🏢 QTIMINDS
📍 Hyderabad