Experience 5+ years of relevant industry experience Education B.E / B.Tech (Required) M.E / M.Tech (Preferred) Key Responsibilities Design and implement RTL using VHDL Develop and debug FPGA-based SDR systems using Xilinx Vivado Work on communication system design (Drone detection, DSSG) Perform timing analysis, XDC constraints, and timing closure Implement DSP blocks and signal processing algorithms Work with communication protocols (Ethernet, high-speed interfaces) Integrate FPGA with RF front-end (ADC/DAC, AD9361/AD9364) Support verification (UVM preferred) Debug hardware using oscilloscope and logic analyzer Use Python for automation and testing Collaborate with RF, hardware, and software teams Required Skills Strong VHDL / RTL design expertise Good understanding of digital logic and communication systems Hands-on experience with Xilinx Vivado Knowledge of timing closure and FPGA constraints Familiarity with DSP and SDR-based system design Basic knowledge of drone RF signals / detection Experience in lab debugging Valuable communication and problem-solving skills

📌 FPGA Engineer III (Chennai)
🏢 Big Bang Boom Solutions Private
📍 Chennai