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About this Opportunity
Join Ericsson's cutting-edge journey to shape the future of 5G networks As a Low-Power Physical Design Engineer, you'll work on pioneering digital ASIC designs vital to Ericsson's mobile network infrastructure. Our team, responsible for the final critical stage of chip design before fabrication, thrives on Lean and Agile principles, promoting close collaboration, daily progress-sharing, and continuous improvement. If you're passionate about advanced technology and ready to make a meaningful impact in telecom, this role is crafted just for you.

At Ericsson, we support your growth, offering opportunities to advance your skills while contributing to game-changing 5G/6G technologies. Here, you'll find a supportive, creative environment focused on quality, teamwork, and career development. Join us and help shape the future of telecom

We are hiring a Low-Power Physical Design Engineer to own chip-level power estimation, analysis, and signoff using Synopsys PrimePower (PTPX) on high-performance, power-constrained SoC designs at advanced process nodes.



You will define and drive power closure methodology, coordinate with RTL, physical design, and architecture teams to meet power budgets, and contribute to synthesis and STA flows as a secondary responsibility. This role is critical to the chip's power-performance story from early RTL through tape-out.

What you will do:

Dynamic Power Analysis
• Own dynamic power analysis using Synopsys PrimePower (PTPX) across all design modes, workloads, and PVT corners.
• Generate, annotate, and validate switching activity files (SAIF / VCD) from RTL and gate-level simulations for accurate power estimation.
• Define representative workload scenarios and activity vectors for meaningful power measurement across use cases (active, idle, burst).
• Perform clock-domain-level, block-level, and full-chip dynamic power breakdowns; identify high-power contributors and drive optimization.
• Collaborate with R

📌 Senior Engineer (India)
🏢 Ericsson
📍 India