15 Aug
|
Weekday AI
|
Bengaluru
15 Aug
Weekday AI
Bengaluru
This role is for one of the Weekday's clients
Min Experience: 6+ years
Location: Bengaluru
JobType: full-time
We are seeking an experienced ASIC RTL Design Engineer with 6–10 years of hands-on experience in RTL design, SoC development, and design verification methodologies. The ideal candidate will have strong expertise in developing robust, synthesizable RTL and a deep understanding of Lint, Clock Domain Crossing (CDC), and SoC integration. You will work closely with architecture, verification, physical design, and other cross-functional teams to deliver high-quality ASIC designs from specification through implementation.
Key Responsibilities
Design, develop, and maintain high-quality, synthesizable RTL for complex ASIC/SoC designs using Verilog/SystemVerilog.
Translate architectural and microarchitectural specifications into productive and scalable RTL implementations.
Perform comprehensive Lint analysis, identify RTL coding issues, and drive corrective actions to ensure clean and maintainable designs.
Analyze and resolve Clock Domain Crossing (CDC) issues,
including synchronization, clock-domain interfaces, and metastability-related concerns.
Contribute to SoC integration, including integrating IPs, subsystems, interfaces, clocks, resets, and interconnect components.
Work with design and verification teams to define interfaces, integration requirements, and functional behavior.
Debug RTL issues using simulation, waveform analysis, and relevant EDA tools.
Review RTL and design documentation to ensure compliance with architectural and coding standards.
Participate in design reviews, code reviews, and technical discussions with cross-functional engineering teams.
Collaborate with verification engineers to develop verification strategies, identify corner cases, and resolve functional issues.
Support synthesis, timing, and implementation teams by ensuring RTL meets quality, performance, and integration requirements.
Investigate design issues throughout the ASIC develop
📌 Asic RTL Design Engineer (Bengaluru)
🏢 Weekday AI
📍 Bengaluru