?Job Title: DFT Engineer
?Experience Required: 3 to 15 Years
?Annual CTC Budget: ₹1,500,000 - ₹5,000,000 LPA
?Location: Bangalore, India

⚠️MANDATORY CRITICAL MATCH CRITERIA:
✅Experience: 3 to 15 years of dedicated experience in DFT engineering. Minimum 2 years of stability in previous organization required.
✅Education: B.E. / B.Tech / M.E. / M.Tech in Electronics/Electrical Engineering or equivalent field. ✅Core Skills: BSCAN, MBIST, Scan Insertion, ATPG Pattern Generation, TDF/Stuck-at Fault Models, and Post-Silicon Bring-up.
✅Software/Tools: Hands-on proficiency in Cadence, Synopsys, or Siemens Tessent DFT tools (VCS, NCSim, Xcelium).
✅Communication: Exceptional English communication skills for cross-functional and client coordination. ✅Logistics: Hybrid / Onsite model located in Bangalore, India.

➡️Position Overview Drive SoC-level Design for Testability (DFT) implementation, pattern validation, and post-silicon bring-up for complex semiconductor designs. Execute end-to-end DFT flows while leading cross-functional integration and test mode timing constraints signoff.





?Core Responsibilities
✔️DFT Architecture: Execute Scan Insertion, MBIST, and BSCAN setup using Cadence, Siemens Tessent, or Synopsys tool suites.
✔️ATPG & Coverage: Perform ATPG pattern generation, TDF/Stuck-at/IDDQ fault modeling, and implement coverage improvement techniques.
✔️Simulations & Debug: Conduct zero-delay and SDF timing simulations with waveform debug using VCS, NCSim, or Xcelium.
✔️SoC Integration: Handle OCC/OPCG insertion, EDT/Compression logic, and clock module setup for high-speed scan modes.
✔️Timing & Post-Silicon: Provide test mode timing constraints to STA/PD teams and assist post-silicon bring-up with ATE shmoo plot analysis.

How to Apply ? Please click the "Apply" button directly on this platform and ensure you accurately complete the mandatory screening questions. Applications with incomplete screening responses or profiles failing to meet the baseline experience metric

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