ASIC Digital Design, Staff Engineer (Bengaluru)

ASIC Digital Design, Staff Engineer (Bengaluru)

15 Aug
|
Synopsys
|
Bengaluru

15 Aug

Synopsys

Bengaluru

We Are:At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are:

You are a passionate and detail-oriented ASIC Digital Design professional who thrives in high-tech, fast-paced environments. With a strong foundation in Design-for-Testability (DFT) methodologies, you enjoy taking ownership of complex challenges and delivering reliable, high-quality results. You are eager to collaborate with diverse, global teams and are driven by a desire to continuously learn and grow within the semiconductor industry. Your expertise in scan insertion, ATPG, and scan STA is matched by your ability to adapt to current tools and technologies. You value open communication, inclusivity, and knowledge sharing,



and you excel at translating intricate technical concepts into actionable solutions. As a proactive problem solver, you are comfortable navigating ambiguity and take pride in mentoring junior engineers while contributing to collective team success. You are committed to upholding Synopsys' culture of innovation, integrity, and excellence, and you are excited about building next-generation semiconductor products that fuel advances in AI, automotive, and beyond.

What You'll Be Doing:

Lead and execute scan insertion and ATPG (Automatic Test Pattern Generation) flows for complex ASIC designs.
Work closely with RTL and Verification teams to ensure DFT requirements are integrated early in the design cycle.
Analyze and resolve DFT-related issues using tools such as Spyglass DFT, ensuring robust test coverage and manufacturability.
Perform scan STA (Static Timing Analysis) to validate timing closure and optimize testability paths.
Collaborate wi

📌 ASIC Digital Design, Staff Engineer (Bengaluru)
🏢 Synopsys
📍 Bengaluru

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