_Job Responsibilities: _
- _Verification of complex designs such as accelerators/ datapath IP, processor core subsystems, complex interfaces/ protocols such as DDR/ Ethernet/ USB etc using leading edge methodologies like UVM & Formal DV _:
- _Architect the testbench and develop the verification environment in UVM and Formal based verification approaches _
- _Define testplan, tests and verification methodology for block / sub-system level verification. Work with design team in generating test-plans and closure of code and functional coverage. Integrate the block testbench at sub-system level UVM setting and verify integration. Interact with analog co-sim and firmware team in enabling toplevel chip verification aspects _
- _Package verification environment for Digital IP for seamless integration into verification flow at different stages of execution _
- _Evaluate 3rd party IPs on key qualitative aspects such as design quality, robustness of Design Verification (DV) practice, ease of DV environment integration and make recommendations.
Establish evaluation flows for home-grown & 3rd party IPs for consistent benchmarking of DV evaluation _
- _Build expertise on complex interfaces, peripherals & protocols such as DDR, Ethernet, eMMC/ SD, MIPI, Display Port, HDMI, PCIe, high speed D2D _
_Position Requirements: _
- _Minimum B.E./ B.Tech degree in Electrical/Electronics/Computer science _
- _6 - 10 years experience in design verification with UVM and constrained random, coverage-based verification approaches _
- _Strong understanding of DV concepts with an eye on developing scalable DV environment architecture that realizes first pass DV success _
- _Experience with translating Design Verification (DV) requirements such as test plans into a robust DV workplace and generate coverage metrics for demonstrating DV convergence _
- _Experience with AI tools in DV _
- _Excellent debugging and analytical skills _
- _Good interpersonal, teamwork and com