RTL Synthesis Methodology Principal/ Sr Staff Engineer (Bengaluru)

RTL Synthesis Methodology Principal/ Sr Staff Engineer (Bengaluru)

15 Aug
|
Qualcomm
|
Bengaluru

15 Aug

Qualcomm

Bengaluru

Company:
Qualcomm India Private Limited
Job Area:
Engineering Group, Engineering Group > Hardware Engineering
General Summary:
As the Principal Engineer, RTL Synthesis Methodology Lead you will drive the technical direction and deployment of next-generation RTL-to-Gate implementation flows for Qualcomm’s industry-leading SoCs (Snapdragon Mobile, Automotive, Compute, and IoT). You will lead the definition and optimization of synthesis methodologies to maximize Power, Performance, and Area (PPA) while ensuring robust Signoff closure for Synthesis, Low Power, STA, and LEC.
You will partner closely with Design teams (CPU, GPU, Modem, DSP), Physical Design (PD) teams, and major EDA vendors (Synopsys, Cadence) to benchmark, certify, and deploy advanced features like Physical Synthesis, Machine Learning-based optimization, and Unified Low Power flows.
Minimum Qualifications:
• Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 8+ years of Hardware Engineering or related work experience.
OR
Master's degree in Computer Science,



Electrical/Electronics Engineering, Engineering, or related field and 7+ years of Hardware Engineering or related work experience.
OR
PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience.
Key Responsibilities
Methodology Leadership: Lead the definition, development, and deployment of the global RTL Synthesis Reference Flow (Fusion Compiler, Genus) across multiple technology nodes (5nm, 3nm, 2nm and beyond).
PPA Optimization: Drive "RTL2GDS" co-optimization initiatives. collaborate with RTL and PD teams to deliver measurable PPA improvements through advanced synthesis techniques
Low Power Synthesis: Architect and maintain the Low Power (UPF/IEEE 1801) implementation methodology. Drive the flow for Static Low Power checking (CLP/VCLP) and power intent verification from RTL to Netlist.
Signoff Con

📌 RTL Synthesis Methodology Principal/ Sr Staff Engineer (Bengaluru)
🏢 Qualcomm
📍 Bengaluru

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