ASIC RTL Design Engineer

Experience: 5-22 Years
Location: Bangalore
Industry: Leading MNC

Job Description

We are looking for experienced ASIC RTL Design Engineers with strong expertise in SoC Subsystem/IP Design and RTL development.

Key Responsibilities & Skills
- Strong expertise in SoC Subsystem/IP Design.
- Hands-on experience in IP design, subsystem/cluster development, and SoC-level integration using Verilog/SystemVerilog.
- Strong knowledge of RTL quality checks, including Lint and CDC.
- Good understanding of Synthesis and Low-Power Design is an added advantage.
- Strong understanding of AMBA protocols AXI, AHB, ATB, and APB.
- Good understanding of timing concepts.
- Experience with one or more interface protocols:
- PCIe
- DDR
- Ethernet
- I2C / UART / SPI




- Hands-on experience with design and verification tools such as:
- SpyGlass Lint/CDC
- Synopsys Design Compiler (DC)
- Verdi / Xcelium
- Positive scripting knowledge in Shell, Python, Perl, Make, or similar scripting languages.
- Understanding of processor architecture and/or ARM Debug Architecture is an added advantage.
- Ability to debug and resolve issues across multiple subsystems.
- Experience in creating and reviewing design specifications and technical documents.
- Ability to collaborate with Physical Design, Verification, DFT, and Software teams for design queries, debugging, and technical reviews.

📌 ASIC RTL Design Engineer-Bangalore- 5 To 22 Years (Bengaluru)
🏢 SDNA Global
📍 Bengaluru