Analog Design Engineer (Hyderabad)

Analog Design Engineer (Hyderabad)

15 Aug
|
Weekday AI (YC W21)
|
Hyderabad

15 Aug

Weekday AI (YC W21)

Hyderabad

This role is for one of Weekday's clients

Salary range: Rs 600000 - Rs 3000000 (ie INR 6 - 30 LPA)
Min Experience: 2+ years

Location: Hyderabad

JobType: full-time

We are looking for a skilled and motivated
Analog Design Engineer
with 2-10 years of experience in analog and mixed-signal IC design. The ideal candidate will have robust hands-on expertise in designing, simulating, and validating high-performance analog circuits, with particular emphasis on
SerDes, LDOs, and Phase-Locked Loops (PLLs)
.

You will work closely with cross-functional teams including architecture, layout, verification, and system engineering to develop robust, high-performance semiconductor solutions. This role offers an opportunity to contribute to challenging designs across advanced process technologies and take ownership of analog blocks from specification through silicon validation.

Requirements
Key Responsibilities
- Design and develop high-performance analog and mixed-signal circuits for advanced semiconductor applications
- Architect, implement, and optimize SerDes circuits,



including high-speed transmit and receive analog front-end blocks
- Design and analyze Low-Dropout Regulators (LDOs), focusing on stability, transient response, PSRR, power efficiency, and load regulation
- Design and develop Phase-Locked Loops (PLLs), including key blocks such as charge pumps, loop filters, voltage-controlled oscillators, and frequency dividers
- Perform circuit-level simulations to evaluate functionality, performance, power consumption, noise, stability, and process-voltage-temperature (PVT) variations
- Work closely with layout engineers to ensure proper implementation of analog blocks while considering matching, parasitics, noise, and layout-dependent effects
- Participate in design reviews and contribute to circuit architecture, specifications, trade-off analysis, and technical documentation
- Perform post-layout simulations and identify performance degradation caused by parasitic effects

📌 Analog Design Engineer (Hyderabad)
🏢 Weekday AI (YC W21)
📍 Hyderabad

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