- 10 years of industry experience in MixedSignal layout design
- Experience in High Speed SerDes layout development preferably in TSMC 3nm
- Experience in complex high speed analog layout design from schematic including effort estimation area estimation optimizing floorplan routing verifications and signoff
- Experience in leading and managing team of layout engineers
- Experience in reviewing layouts and providing inputs for high quality layout development
- Mentoring and guiding the team for seamless timely execution of project
- Positive at LVSDRC debugging skills and other verifications for lower technology nodes
- Good understanding of Matching EM ESD LatchUp Shielding Parasitic and short channel concepts
- Familiar with EDA tools like Cadence Virtuoso Editor Calibre
- Good interpersonal skills and critical thinking abilities to resolve the issue technically and professionally
- Excellent communication
- Holding Bachelors or Masters degree in electricalElectronic Engineering
Experience (years) : 9+ years
Education Qualification:
BTECH/MTECH in Electrical/Electronics/Computer Science Engineering or Equivalent
📌 Analog Layout (India)
🏢 Mirafra Software Technologies
📍 India
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