FPGA Design & Validation Engineer (Hyderabad)

FPGA Design & Validation Engineer (Hyderabad)

15 Aug
|
Majoris Technologies
|
Hyderabad

15 Aug

Majoris Technologies

Hyderabad

Role: FPGA Design & Validation Engineer

Location: Kokapet, Hyderabad

Work Mode: Work from Office – 5 days/week

Key Requirements

- 5+ years of relevant experience in FPGA Design and Validation
- Hands-on experience validating FPGA designs on physical boards
- Experience with board-level debugging and hardware bring-up
- Hands-on experience using Oscilloscopes for hardware/debugging activities
- Experience with TCL scripting
- Positive understanding of Lint and CDC (Clock Domain Crossing)
- Experience with Spirent or other traffic generator tools is an added advantage
- Knowledge of AI Agents and Prompt Engineering is a plus

The ideal candidate would have a combination of FPGA design, board-level validation, hardware debugging and lab testing experience.

Skills:- RTL, FPGA, Verification and validation and design

📌 FPGA Design & Validation Engineer (Hyderabad)
🏢 Majoris Technologies
📍 Hyderabad

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