Job DescriptionJob Description:
NRole: Senior RTL Design Engineer
NExperience: 6 - 12 Years of Experience
NLocation: Bangalore/ Hyderabad
NWork Mode: Work from office
NRequired Skills
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Experience in Logic design / RTL coding is a must. N
Experience is SoC design and integration for complex SoCs is a must. N
Experience in Verilog/System-Verilog is a must. N
Experience in Multi Clock designs, Asynchronous interface is a must. N
Experience in using thetools in ASIC development such as Lint and CDC. N
Experience in Synthesis/ Understanding of timing concepts is a plus. N
Experience in ECO fixesand formal verification. N
Should have knowledge of AMBA protocols - AXI, AHB, APB, SoC clocking/reset architecture. N
Excellent oral and written communications skills. N
Proactive, creative, curious, motivated to learn and contribute with positive collaboration skills N