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We are seeking enthusiastic, driven, and imaginative individuals to join our networking group. As the owner of networking IP's unit and cluster level verification, you will contribute to projects crafting the future of our datacenter chips and systems. You will gain direct experience of chip working with high-performance queuing and scheduling sub-systems.

What you'll be doing:




You will develop verification components and API's for unit and cluster level test benches. These will verify queuing and scheduling algorithms and designs.
During the course of a project, you will drive the following aspects of verification for your unit:
Architect the testbenches and craft verification environment using Specman language and methodology
Define test plans, tests and verification infrastructure for clusters and systems
Build productive and reusable bus functional models, monitors, checkers, and scoreboards
Implement functional coverage and own unit/cluster level verification closure
Work with architects, designers, FPGA, and post-silicon teams to ensure that your unit is robust

What we need to see:
BTech or MTech in ECE, EE, CSE, or an equivalent degree is required. Candidates should have over 3 years of experience in verification closure of complex units, sub-systems, or SOC level

📌 Verification Engineer Bengaluru
🏢 NVIDIA
📍 Bengaluru