At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
Proficient in Verilog coding and RTL design, data path designs,
Knowledge of RTL checks ex- LINT, SDC, CDC
Familiar with synthesis flow and timing constraints
Experience in writing Verilog testbench and running simulations.
Familiar with any of the interface Protocols like UCIe, PCIe, USB, MIPI(DPHY), HDMI/Display
We’re doing work that matters. Help us solve what others can’t.
📌 Lead Design Engineer Noida
🏢 Cadence Systems
📍 Noida
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