We are looking for an experienced PCIe IP Design Engineer to join our high-performance IP development team. The ideal candidate should have hands-on experience in designing and developing PCI Express (PCIe) IPs, with robust expertise in RTL design, microarchitecture, and high-speed interface protocols. Required Skills
58 years of experience in ASIC/SoC RTL Design.
Strong hands-on experience with PCIe IP Design (Gen4/Gen5/Gen6 preferred).
Expertise in Verilog/SystemVerilog RTL coding.
Robust understanding of PCIe protocol architecture, including:
Transaction Layer (TL)
Data Link Layer (DLL)
Physical Layer (PHY)
LTSSM
Configuration Space
BAR, MSI/MSI-X
DMA concepts
Experience in RTL microarchitecture, implementation, and integration.
Good knowledge of digital design fundamentals and ASIC front-end design flow.
Experience with lint, CDC, synthesis, STA, and low-power design considerations.
Familiarity with AMBA protocols (AXI/AHB/APB) and high-speed interfaces.
Robust debugging and problem-solving skills.Role & responsibilities

Preferred candidate profile

📌 Pcie Ip Design Engineer Bengaluru
🏢 Sivaltech
📍 Bengaluru