Our vision is to transform how the world uses information to enrich life for all.

Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.

Key Responsibilities

Place & Route / Physical Design
Hands on experience in custom layout is added requirement
place-and-route (P&R;) and layout closure for digital or semi‑custom blocks.
Develop floorplans, power grids, and placement strategies
Leverage AI‑assisted RTL‑to‑GDS flows for early PPA prediction, congestion awareness, and faster convergence
Execute placement, CTS, and routing using industry‑standard PnR tools
Drive timing, power, and congestion closure
Fix DRC, LVS, antenna, EM/IR violations to achieve signoff‑clean designs
Apply AI‑guided ECO generation and prioritization for timing, power, and functional fixes.
Collaborate with RTL, DFT, STA, and signoff teams during the design cycle
Support tape‑out and post‑silicon debug activities





Static Timing Analysis (STA)
Perform full‑chip and block‑level STA across all modes, corners, and scenarios
Analyze and close setup, hold, recovery, removal, and pulse width checks
Perform pre‑CTS and post‑CTS timing analysis
Work closely with PnR teams to drive timing closure strategies
Handle OCV/AOCV/POCV, CRPR, and clock uncertainty modeling
Analyze and debug timing paths, false paths, and multicycle paths
Perform timing ECO recommendations and validate fixes
Generate and review timing reports for signoff
Support timing signoff using foundry‑qualified methodologies
Leveraging Artificial Intelligence

About Micron Technology, Inc.

We are an industry leader in cutting-edge memory and storage solutions transforming how the world uses information to enrich life for all. With a relentless focus on our customers, technology leadership, and manufacturing and operational excellence, Mi

📌 Senior Layout Engineer – Dpg Lpddr Hyderabad
🏢 Micron
📍 Hyderabad