Asic Design Verification Engineer, Silicon Bengaluru

Asic Design Verification Engineer, Silicon Bengaluru

15 Aug
|
Google
|
Bengaluru

15 Aug

Google

Bengaluru

Minimum qualifications:
Bachelor's degree in Electrical Engineering or Computer Science, or equivalent practical experience.
8 years of design verification experience.
Experience verifying digital logic at RTL using SystemVerilog and UVM for ASICs.
Experience verifying digital systems using standard IP components/interconnects (e.g., microprocessor cores, caches, Coherency, hierarchical memory subsystems, DDR/LPDDR).

Preferred qualifications:
Master's degree in Electrical Engineering or Computer Science with 10 years of relevant work experience.
Experience creating and using verification components and settings in a standard verification methodology such as UVM.
Experience with performance verification of ASICs and ASIC components and experience with ASIC standard interfaces and memory system architecture, LPDDR.
Experience with verification techniques, System Verilog Assertions (SVA) and assertion-based verification using Industry leading formal tools.
Experience with GLS, low-power DV, and support of SOC DV.
Experience in formal verification.





About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

Google's mission is to organize the world's information and make it universally accessible and helpful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop recent technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

Responsibilities
Plan the verification of complex Memory Subsystem IPs at IP and Subsystem level by fully understanding the design specification and inte

📌 Asic Design Verification Engineer, Silicon Bengaluru
🏢 Google
📍 Bengaluru

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