Hi All,

We are #hiring for a #SeniorAnalog_Layout Engineer, worked RF, PMIC, regulators on 45nm and above technologies, based in Bengaluru, WFO. Responsibilities include the optimization of analog and mixed-signal layouts, #PowerMosfets , #ESD constraints, #BJTs , #HigherVoltage , #HigherCurrent IP's independently and sign off with verification.

Qualifications

Proficiency in #Layout /mask design with an experience from 7+ to 12 years of experiences.

Expert knowledge in Layout Design Techniques #ESD compliance, power devices, #RF blocks and higher voltages-current blocks.

Robust skills in debugging Parasitic Extraction, crosstalk, EMIR mitigation, and physical verification (DRC, LVS, PM & Signoff checks).

Experience with 180nm to 45nm technology nodes, #BiCMOS , hashtag

#BJTs .

Bachelor’s or Master’s degree in ECE & EEE.

Interested candidates please send resume to [email protected] .

hashtag

#analog_layout , #BCD_process , #IC_Design , #AMS_Layout , #Analoglayout , #Senior_layout_design ,

#DRC , #LVS

📌 Senior Analog Layout_PMIC (Bengaluru)
🏢 ASICtronix and TechSoft
📍 Bengaluru