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Job Title:
DFT Engineer

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Experience Required:
3 to 15 Years

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Annual CTC Budget:
₹1,500,000 - ₹5,000,000 LPA

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Location:
Bangalore, India

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MANDATORY CRITICAL MATCH CRITERIA:

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Experience:
3 to 15 years of dedicated experience in DFT engineering. Minimum 2 years of stability in previous organization required.

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Education:
B.E. / B.Tech / M.E. / M.Tech in Electronics/Electrical Engineering or equivalent field. ✅
Core Skills:
BSCAN, MBIST, Scan Insertion, ATPG Pattern Generation, TDF/Stuck-at Fault Models, and Post-Silicon Bring-up.

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Software/Tools:
Hands-on proficiency in Cadence, Synopsys, or Siemens Tessent DFT tools (VCS, NCSim, Xcelium).

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Communication:
Exceptional English communication skills for cross-functional and client coordination. ✅
Logistics:
Hybrid / Onsite model located in Bangalore, India.

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Position Overview
Drive SoC-level Design for Testability (DFT) implementation, pattern validation, and post-silicon bring-up for complex semiconductor designs.



Execute end-to-end DFT flows while leading cross-functional integration and test mode timing constraints signoff.

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Core Responsibilities

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DFT Architecture:
Execute Scan Insertion, MBIST, and BSCAN setup using Cadence, Siemens Tessent, or Synopsys tool suites.

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ATPG & Coverage:
Perform ATPG pattern generation, TDF/Stuck-at/IDDQ fault modeling, and implement coverage improvement techniques.

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Simulations & Debug:
Conduct zero-delay and SDF timing simulations with waveform debug using VCS, NCSim, or Xcelium.

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SoC Integration:
Handle OCC/OPCG insertion, EDT/Compression logic, and clock module setup for high-speed scan modes.

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Timing & Post-Silicon:
Provide test mode timing constraints to STA/PD teams and assist post-silicon bring-up with ATE shmoo plot analysis.

How to Apply
? Please click the "Apply" button directly on this platform and ensure you accurately complete the mandatory screening questions. Applications with incomplete screening responses or profiles failing to meet

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