This role is for one of our clients
Industry: Information Technology & Services

Seniority level: Mid-Senior level

Min Experience: 5+ years

Location: Bengaluru, Telangana, Hyderabad, Telangana, India, Karnataka

JobType: full-time

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We are seeking an experienced
DFT Engineer
with
5–20 years of industry experience
to drive the design-for-test strategy and implementation for complex ASIC/SoC designs. The ideal candidate will have robust hands-on expertise in
ATPG and Scan
, with a solid understanding of test architecture, fault coverage, test pattern generation, and DFT verification.





You will work closely with RTL, Physical Design, Verification, and Product Engineering teams to develop robust, production-ready test solutions while ensuring high test coverage, quality, and manufacturability.

Requirements
Key Responsibilities
- Define and implement DFT architectures for complex ASIC/SoC designs
- Develop and integrate Scan-based DFT structures across blocks and top-level designs
- Develop, run, and debug ATPG flows for stuck-at, transition, and other relevant fault models
- Analyze ATPG coverage, fault reports, pattern quality, and test compression results
- Debug ATPG failures and identify design, constraint, or test-logic issues
- Work with RTL and design teams to resolve DFT-related implementation and verification issues
- Perform DFT rule checks and ensure test structures meet project requirements
- Support scan insertion, scan-chain verification, chain balancing, and sca

📌 Design-for-Test (DFT) Engineer (Hyderabad)
🏢 Weekday (YC W21)
📍 Hyderabad