Job description

Urgent Hiring

Greetings from Sunrise Biztech Systems Pvt. Ltd.

We are hiring for one of our reputed clients for the following position. If you're interested and your experience matches the requirement, we'd love to hear from you.

Job Title: RTL Design Engineer 2

Work Location: Hyderabad

Contract Duration: 12 Months

Key Responsibilities:
- Develop synthesizable RTL using Verilog/SystemVerilog.
- Design and integrate IPs/subsystems using AXI, AXI4-Lite, AHB, and APB protocols.
- Handle clock/reset architecture, address mapping, and configuration integration.
- Drive Lint, CDC, RDC, X-propagation, structural checks, and synthesis signoff.
- Debug and resolve RTL quality violations and ensure clean design handoff.




- Perform RTL reviews and ensure protocol/methodology compliance.
- Develop Python/Perl/Tcl automation for quality checks, regressions, and reporting.
- Collaborate with architecture, verification, and implementation teams to ensure production-ready RTL.

Must-Have Skills:
Verilog, SystemVerilog, RTL Design, AXI/AHB/APB, Lint, CDC, RDC, Synthesis, RTL Signoff, Subsystem Integration, Scripting/Automation.

Education: BE/B.Tech/M.Tech in Electronics, Electrical, VLSI, or related field.

📌 Rtl Design Engineer 2307 (Hyderabad)
🏢 Sunrise BizTech Systems
📍 Hyderabad