Job DescriptionLead RTL Design Engineer (ASIC)
NLocation: Chennai, Tamil Nadu
NExperience: 6 to 9 Years
NJob Description
n6to 9 Years of experience in Synthesis, Constraints and interface timing Challenges. Good knowledge of Power is preferable.
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- Solid Domain Knowledge on RTL Design, implementation, and Timing analysis. N
- Experience with RTL coding using Verilog/VHDL/System Verilog. N
- Experience in micro-architecture & designing cores and ASICs. N
- Familiar with the Synthesis, Formal Verification, Linting, CDC, Low Power, UPFs, etc. N
- Exposure in scripting (Pearl/Python/TCL). N
- Strong debugging capabilities at Synthesis, timing analysis & implementation N
- Collaborate closely with cross-function team to research, design and implement performance, constraints and power management strategy for product roadmap. N




- Good team player. Need to interact with the other teams/verification engineers proactively. N
- Ability to debug and solve issues independently. N

nAbout Company
nACL Digital, part of the ALTEN Group, is a trusted AI-led, Digital & Systems Engineering Partner driving innovation by designing and building intelligent systems across the full technology stack — from chip to cloud. By integrating AI and data-powered solutions, we help enterprises accelerate digital transformation, optimize operations, and achieve scalable business outcomes. Partner with us to turn complexity into clarity and shape the future of your organization.

📌 Lead Rtl Design Engineer (India)
🏢 ACL Digital
📍 India