Description
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Experience: 5+ yrs
Location: Bengaluru, Karnataka, India, India
Job Type: Full-time

We are seeking an experienced Static Timing Analysis (STA) Engineer to drive timing closure and sign-off activities for advanced SoC designs across cutting-edge semiconductor technology nodes. This role is ideal for professionals with deep expertise in Static Timing Analysis, timing optimization, and sign-off methodologies, who thrive in a cooperative VLSI development environment.
As an STA Engineer, you will be responsible for performing comprehensive timing analysis, driving timing convergence, implementing Engineering Change Orders (ECOs), and working closely with Physical Design, Synthesis, and Clock Tree Synthesis (CTS) teams to ensure successful tape-outs. You will play a critical role in delivering high-performance, reliable, and timing-clean semiconductor designs.

Requirements
Key Responsibilities
- Perform block-level and full-chip Static Timing Analysis (STA) for complex,



high-performance SoC designs.
- Drive timing closure throughout the design lifecycle, including pre-layout and post-layout stages.
- Analyze and resolve setup, hold, recovery, removal, maximum transition, maximum capacitance, and fanout violations.
- Execute MCMM (Multi-Corner Multi-Mode) timing analysis and optimization to ensure robust design performance.
- Collaborate closely with Physical Design, Synthesis, CTS, Routing, and ECO teams to achieve timing convergence.
- Generate, review, and interpret timing reports while identifying and resolving critical timing paths.
- Implement and validate ECOs to improve timing performance and support design optimization.
- Support timing sign-off activities, including signal integrity (SI) analysis and low-power timing verification.
- Contribute to successful tape-outs by ensuring compliance with timing, quality, and design requirements.
- Develop

📌 Static Timing Analysis (Bengaluru)
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📍 Bengaluru