Please Note:
1. If you are a first time user, please create your candidate login account
before you apply for a job. (Click Sign In > Create Account)
2. If you already have a Candidate Account, please Sign-In before you apply.
JOB DESCRIPTION:
In this role, the Engineer will apply and lead Broadcom's proven design
methodology and milestone flow to meet rigorous criteria for achieving
Right-First-Time silicon. The STA Engineer is responsible for ensuring robust
timing closure and signoff readiness for block- and full-chip designs across all
modes and corners. This role owns timing constraint development and validation,
performs detailed setup/hold and variation-aware analysis, and partners closely
with Synthesis, CTS, Physical Design, and Design teams to debug violations and
drive ECO-based optimizations through tape out.
Responsibilities include, but are not limited to:
- Perform full-chip and block-level Static Timing Analysis (STA) across all
modes and corners.
- Analyze and debug setup, hold, recovery, removal, clock gating, and signal
integrity-related timing violations.
- Work closely with Physical Design, Synthesis, CTS, and Design teams to
achieve timing closure.
- Develop and maintain timing constraints including SDC creation, validation,
and signoff readiness.
- Drive timing closure through ECO implementation and timing optimization.
- Analyze timing impact due to process, voltage, and temperature variations.
- Support timing signoff for pre-layout and post-layout stages.
- Perform cross-functional reviews for timing convergence and provide
recommendations.
- Generate timing reports and communicate closure status to project
stakeholders.
Minimum Qualifications:
- MSEE/MSCS with 10+ years of experience, or BSEE/BSCS with 12+ years of
experience in Static Timing Analysis (STA) and timing closure for block and/or
full-chip designs.
- Robust understanding of CMOS fundamentals, timing concepts, and
semiconductor design flow.
- Hands-on experience in setup/
📌 Physical Design Engineer (Pune)
🏢 Broadcom
📍 Pune