Job Title: Verification Engineer – Digital

Location: Bangalore (Work From Office)
Employment Type: Full-time
Experience Required: 5–13 years

Job Overview

We are seeking a skilled and detail-oriented Digital Verification Engineer with a solid background in mixed-signal devices and expertise in SystemVerilog and UVM methodologies. The ideal candidate will have hands-on experience in developing verification environments and driving block-level to chip-level verification efforts in a fast-paced engineering environment.

Key Responsibilities

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Develop verification environments and testbenches for block, subsystem, and chip-level verification using SystemVerilog/UVM.

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Collaborate closely with design teams to integrate design changes into verification flows.

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Perform simulations and debug using gate-level netlists across multiple PVT corners.

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Handle VCD generation for power analysis and contribute to DFT validation and ATPG simulations.

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Apply code and functional coverage metrics to drive verification completeness.

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Write and maintain scripts using Perl, Python, or Shell to support automated verification workflows.

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Coordinate with analog and architecture teams for mixed-signal integration and model handling.

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Support bring-up and characterization lab activities, including FPGA-based validation platforms.

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Provide support in resolving customer debug queries and delivering timely technical solutions.

Key Requirements

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Bachelor’s or Master’s degree in Electrical, Electronics, or a related technical discipline.

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5–13 years of hands-on experience in digital verification.

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Strong expertise in SystemVerilog, UVM, and scripting languages.

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Solid understanding of digital fundamentals, DFT concepts, and mixed-signal integration.

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Proven debugging and problem-solving skills.

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Excellent team collaboration and communication abilities.

📌 Verification Engineer – Digital (Bengaluru)
🏢 VLaunchU
📍 Bengaluru