Job Description – Design Verification Engineer (5+ Years)

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Location:
Bangalore / Noida / Pune / Ahmedabad

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Experience:
4+ Years

Job Responsibilities
- Develop and execute comprehensive verification plans for complex SoC/ASIC designs.
- Build reusable, scalable verification environments using SystemVerilog and UVM.
- Develop testbenches, test cases, assertions (SVA), and functional coverage models.
- Perform block-level and SoC-level verification to ensure design functionality and quality.
- Debug RTL issues, analyze simulation failures, and work closely with Design and Architecture teams to resolve them.
- Verify industry-standard protocols such as AXI, AHB, APB, PCIe, USB, Ethernet, DDR, MIPI, or similar.
- Perform regression testing, coverage closure, and verification sign-off.
- Collaborate with Emulation, Firmware, and Physical Design teams during project execution.

Required Skills
- 5+ years of hands-on experience in ASIC/SoC Design Verification.
- Solid expertise in
SystemVerilog
and
UVM
methodology.




- Experience in developing reusable verification components (UVCs), scoreboards, monitors, and sequences.
- Strong debugging skills using simulators such as
Synopsys VCS
,
Cadence Xcelium
, or
Siemens Questa
.
- Experience with functional coverage, code coverage, assertions (SVA), and regression management.
- Good understanding of RTL design, ASIC design flow, and digital design fundamentals.
- Proficiency in scripting using
Python
,
Perl
, or
Tcl
.
- Excellent knowledge of protocols such as
AXI/AHB/APB
, with exposure to PCIe, USB, DDR, Ethernet, or MIPI being an added advantage.

Preferred Skills
- Experience with SoC-level verification and subsystem integration.
- Exposure to Formal Verification, Emulation (Palladium/Protium/Veloce), or low-power verification (UPF/CPF).
- Experience working on advanced technology nodes and successful tape-out projects.

📌 Senior Design Verification Engineer (Bengaluru)
🏢 eInfochips (An Arrow
📍 Bengaluru