Memory Layout Engineer (Bengaluru)

Memory Layout Engineer (Bengaluru)

16 Aug
|
Spatial Alphabet
|
Bengaluru

16 Aug

Spatial Alphabet

Bengaluru

Job Title: Memory Layout Engineer

Experience: 4–8 Years

Job Location: Bengaluru

Job Summary

We are seeking an experienced Memory Layout Engineer to work on advanced semiconductor technologies

including TSMC/Samsung 2nm, 3nm, 5nm, 7nm, and GlobalFoundries (GF) nodes. The ideal candidate will have

robust expertise in custom memory layout, physical verification, and memory integration for high-performance

SRAM/DRAM compiler IPs.

You will collaborate with Circuit Design, Physical Design, Verification, PDK, and Methodology teams to deliver

optimized, manufacturable, and silicon-ready memory layouts.

Key Responsibilities

 Develop custom layouts for memory blocks including control logic, sense amplifiers, I/O blocks, bit cell

arrays, row/column decoders, and peripheral circuits.

 Perform top-level memory integration for SRAM/DRAM compiler IPs.

 Execute and resolve DRC, LVS, Density, ERC, and Physical Verification issues.

 Optimize layouts for area, power, performance, yield, and manufacturability.

 Address IR Drop and Electromigration (EM) challenges in memory layouts.





 Work closely with Circuit Design teams to ensure layout matches design intent.

 Ensure compliance with advanced technology node design rules and DFM guidelines.

 Collaborate with PDK and Methodology teams for process updates and layout improvements.

 Support layout sign off and tape-out activities.

Required Skills

 4–8 years of experience in Memory Layout for ASIC/VLSI designs.

 Hands-on experience in layout of:

o Sense Amplifiers

o Control Logic

o Bitcell Arrays

o Row/Column Decoders

o I/O Blocks

o Memory Peripheral Circuits

 Strong understanding of SRAM, DRAM, and Memory Compiler IPs.

 Experience with Top-Level Memory Integration.

 Expertise in:

o DRC

o LVS

o Density Verification

o Physical Verification

o Physical Closure

 Knowledge of IR Drop and Electromigration (EM) analysis.

 Experience with advanced technology nodes:

o TSMC/Samsung – 2nm, 3nm, 5

📌 Memory Layout Engineer (Bengaluru)
🏢 Spatial Alphabet
📍 Bengaluru

Reply to this offer

Impress this employer describing Your skills and abilities, fill out the form below and leave Your personal touch in the presentation letter.

Subscribe to this job alert:

Get the latest job offers by email for: memory layout engineer (bengaluru) / bengaluru