Minimum Qualifications:

Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. ORMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. ORPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.

PD JD:
- Thorough knowledge of the ASIC designs Place and Route flow and methodology.
- Hands-on experience in executing complete PD ownership from netlist to GDS2 including HM level PV, LEC, low-power checks and PDN, STA closure
- Hands-on experience in Voltage Islands and low power methodologies, flows and implementation.




- Robust background in debugging Congestion and CTS issues.
- Expertise in PnR tools (Innovus/Fusion compiler) and flow.
- Familiarity with Sign-off(PV/PDN/STA/FV/CLP/Scan-DRC(tk)) methodology and tools.
- Understand and implement improving existing methodologies and flows.
- Proficient in scripting languages (TCL,PERL,PYTHON).
- Self-starter and highly motivated
- To have working experience in global team environment.
- To be effectively communicate the status and issues of respective owned Tasks
- 4-10 yrs of experience in physical design including floorplanning, PNR, CTS and signoff checks

📌 Physical Design Engineer, Sr. (Hyderabad)
🏢 Qualcomm
📍 Hyderabad