This position is for Senior Level STA Engineer who will oversee full chip and/or subsystem level STA convergence from early stages to signoff. Taking part in top level floorplan and clock planning. Work closely with logic design and DFT engineers to define and implement constraints for the various work modes including their optimization of runtime.

Key Responsibilities

Solid experience in ASIC timing constraints generation, validation and timing closure.
Expertise in Primetime and timing eco (physical aware) using PT-DMSA - full chip and block level
Experience in IO Timing/ interface budgeting / process margins / corner definitions
Familiarity with DFT
Proficient in scripting language (TCL/python).
excellent timing and flow debugging skills
Experience in ECO generation flow for RTL, pre-physical and post route implementation considering timing, congestion and logic equivalence.
Automation to improve PPA (power/performance/area) and ensure a high-quality design environment for SOC.
Proficient in scripting language (TCL/python).
Hands on experience in reference flows,



excellent debugging skills.

Academic Credentials

Bachelors or Master's degree in Computer/Electronics/Electrical Engineering

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JD for Physical Design Timing

Relevant Experience 07-11 Years – L3

Role : Lead Physical Design Timing Engineer

Key Responsibilities

This position is for Senior Level STA Engineer who will oversee full chip and/or subsystem level STA convergence from early stages to signoff. Work closely with logic design and DFT engineers to define and implement constraints for the various work modes.

Key Responsibilities

Strong experience in ASIC timing constraints generation, validation and timing closure.
Expertise in Primetime and timing eco (physical aware) using PT-DMSA - full chip and block level
Experience in IO Timing/ interface budgeting / process margins / corner definitions
Familiarity with DFT

📌 Senior Principal Engineer (Bengaluru)
🏢 Larsen and Toubro
📍 Bengaluru